1. Field of the Invention
The present invention relates to an output driving circuit, and more particularly, to an output driving circuit capable of reducing the inductive current effect and preventing EMI accordingly.
2. Description of the Prior Art
A class D power amplifier offers advantages of small size, high efficiency, and energy savings so that the class D power amplifier has widely been applied in various electronic products, such as notebooks, LCD monitors, mobile phones, and multimedia players, etc.
The class D amplifier adopts a Pulse-Width Modulation (PWM) technology for signal modulation. However, such switching operation of the class D amplifier can easily cause an electromagnetic Interference (EMI) problem. Please refer to FIG. 1, which is a schematic diagram of an output driving circuit 10 according to the prior art. The output driving circuit 10 is utilized for a class D power amplifier. The output driving circuit 10 includes a non-overlapping signal generation unit 102, a first pre-driving circuit 104, a second pre-driving circuit 106, and an output stage 108. The non-overlapping signal generation unit 102 is utilized for generating a first non-overlapping signal S1 and a second non-overlapping signal S2 according to a PWM type input signal S1 in order to prevent transistors of the output stage 108 from conducting at the same time. The first pre-driving circuit 104 is utilized for generating a first pre-driving signal SP1 according to the first non-overlapping signal S1 to control an on/off state of a high-side switch HS of the output stage 108. The second pre-driving circuit 106 is utilized for generating a second pre-driving signal SP2 according to the second non-overlapping signal S2 to control an on/off state of a low-side switch LS of the output stage 108. As shown in FIG. 1, a bootstrap configuration is adopted to the output driving circuit 10, so that a bootstrap power supply BS is provided to the first pre-driving circuit 104 and a power supply VDD is provided to the second pre-driving circuit 106. Furthermore, the first pre-driving circuit 104 and the second pre-driving circuit 106 are respectively an inverter circuit with a combination of p-type and n-type metal-oxide-semiconductor (MOS) transistors. The output stage 108 outputs an output signal SO via an output end OUT to a load 110. The interconnections of the units of the output driving circuit 10 are as shown in FIG. 1 and further description is omitted for brevity.
In general, through the control of the non-overlapping signal generation unit 102, both the high-side switch HS and low-side switch LS are able to be switched into an off state before either one switch is turned on, and there is a short time interval, called non-overlap time, in which both the switches HS and LS are in the off state. IF the load 110 is an inductive load, such as a speaker, a current called load inductive current in the load 10 cannot change instantaneously during the non-overlap time. In such a condition, the load inductive current must continue to flow so that parasitic diodes of the high-side switch HS and the low-side switch LS may be conducted for serving as discharge paths in order to leak the load inductive current.
For example, please refer to the FIG. 2(A), as the input signal S1 is changed from a low voltage level (Low) to a high voltage level (High), the second pre-driving signal SP2 can be pulled down from the high voltage level. After that, the gate voltage VGSL of the low-side switch LS can be pulled down from the high voltage level accordingly and during the time interval T1, the low-side switch LS is switched into an off state. Furthermore, during the time interval T1, the first pre-driving signal SP1 can be progressively pulled up from the low voltage level. The gate voltage VGSU of the high-side switch HS can be pulled up from the low voltage level later accordingly, and the high-side switch HS is switched into an on state during the time interval T2. In other words, during a short duration of the time interval T1, both the high-side switch HS and high-side switch HS are in the off state, currents in the load 10 cannot change instantaneously, resulting in a load inductive current IL1 flowing at a direction from the load 110 to the output end OUT. In such a condition, the voltage value on the output end OUT will rise up due to the load inductive current IL1 and a parasitic diode PD1 of the high-side switch HS can be conducted accordingly for serving as a current path.
However, when the load inductive current IL1 passes through the parasitic diode PD1, the voltage level on the output end OUT will be suddenly pulled up to the high voltage level. In other words, the output signal SO is switched into the high voltage level rapidly so that the output stage 108 has a very high output slew rate, and the EMI occurs. Similarly, please refer to the FIG. 2(B), as the input signal SI is changed from High to Low, a load inductive current IL2 flowing at a direction from the output end OUT to the load 110 occurs during the non-overlap time, a parasitic diode PD2 of the low-side switch LS can be conducted by the load inductive current IL2 for serving as a current path. Therefore, the voltage level on the output end OUT will be suddenly pulled down to the low voltage level. The output signal SO is rapidly switched into the low voltage level, resulting in a very high output slew rate, and the EMI occurs. In short, the output stage 108 may have a high output slew rate due to the rapid switching of the output signal SO so as to introduce the EMI problem. Moreover, almost all current electronic products are demanded to meet some international EMI standards, such as FCC, CE, etc. Therefore, how to figure out an appropriate solution for reducing the EMI emission generated from the operation of the output driving circuit 10 should be a concern in the progressive circuit design.